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Resource constrained RTL partitioning for synthesis of multi-FPGA designs

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3 Author(s)
Vootukuru, M. ; Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA ; Vemuri, R. ; Kumar, N.

In this paper we address the problem of partitioning register level designs for implementation on multiple FPGAs. The partitioner uses a modified multi-way Fiduccia-Mattheyses algorithm. Cost estimation functions needed by the partitioner to estimate the resources needed by the design on a FPGA have been developed. The methodology for estimation of resources on an FPGA (function generators, flip-flops and CLBs), and partitioning of the design are discussed in detail

Published in:

VLSI Design, 1997. Proceedings., Tenth International Conference on

Date of Conference:

4-7 Jan 1997