By Topic

Optimal clock period for synthesized data paths

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
A. R. Naseer ; Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., New Delhi, India ; M. Balakrishnan ; A. Kumar

For technologies with significant interconnection delays, optimal clock period selection before/during high-level synthesis is not practical. In our approach, we start with a synthesized RTL data path structure, perform place and route and back-annotate the interconnection delays. A set of potentially optimal clock periods are chosen by evaluating `critical' paths to minimize the dead time associated with operations. Finally, the controller costs at these clock periods along with the execution times decide the optimal clock period. Extensive experimental results on data paths synthesized from high-level synthesis benchmarks establish both the utility as well as the efficiency of our approach

Published in:

VLSI Design, 1997. Proceedings., Tenth International Conference on

Date of Conference:

4-7 Jan 1997