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(Quasi-) linear path delay fault tests for adders

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3 Author(s)
B. Becker ; Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany ; R. Drechsler ; S. M. Reddy

We investigate the path delay fault testability of the adder function. A method to reduce the number of tests is presented and applied to several well-known hardware realizations, like the Carry Ripple Adder (CRA) and the the Carry Look Ahead Adder (CLA). Depending on the structure we obtain linear or quasi-linear, i.e. O(n) or O(n log n), respectively, size for a complete test of the whole adder with respect to its timing behavior, thus e.g. making feasible an on-line dynamic test for many adders currently in use

Published in:

VLSI Design, 1997. Proceedings., Tenth International Conference on

Date of Conference:

4-7 Jan 1997