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TSV mutual inductance effect on impedance of 3D stacked on-chip PDN with Multi-TSV connections

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7 Author(s)
Jun So Pak ; EE Dept., KAIST, Daejeon, South Korea ; Jonghyun Cho ; Joohee Kim ; Junho Lee
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This paper anayizes TSV mutual inductance effect on impedance of 3D stacked on-chip PDN with multi-TSV connections. 3D stacked on-chip PDN is composed of many numbers of power/ground (P/G) TSVs and vertically stacked on-chip PDNs. Therefore, power comsumptions and density are very high. Vertical P/G current flows are tied up to TSV inductance. TSV inductance increases impedance of 3D stacked on-chip PDN. TSV inductance variation depending on TSV mutual inductance effects is analyzed by the proposed P/G TSV model and the proposed P/G multi-TSV model. As the distance between power and ground TSVs increases, TSV mutual inductance decreases. While TSV inductance increases. The increased TSV indcutance makes 3D on-chip PDN impedance enlarged in low frequency range around 1 GHz. In case of P/G multi-TSVs, TSV mutual inductance effects are changed depending on numbers of neighbor power and ground TSVs and where they are. The same epectric property as a neighbor TSV (i.e., Power-Power or Ground-Ground) makes the sign of TSV mutual inductance positive and increases both TSV inductances. Analogously considering all neighbor TSVs, TSV indcutances can be determined and have many cases. TSV inductance in P/G multi-TSV is analyzed considering various P/G multi-TSV arrangements. P/G multi-TSV inductance effects appear over 1 GHz in 3D stacked on-chip PDN impedance.

Published in:

CPMT Symposium Japan, 2010 IEEE

Date of Conference:

24-26 Aug. 2010