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Flags and algebra for sequential circuit VNR path delay fault test generation

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3 Author(s)
M. K. Srinivas ; CAIP Center, Rutgers Univ., Piscataway, NJ, USA ; M. L. Bushnell ; V. D. Agrawal

We present a new test generator for path delay faults in sequential circuits to generate validatable non-robust (VNR) tests. We use Boolean flags to generate VNR tests dynamically during the generation of robust tests, by relaxing certain off-path input requirements to those of non-robust tests. Results show that VNR tests provide a 10% improvement over the robust coverage of path delay faults in the sequential circuits considered. We adopt a 13-valued algebra to generate robust tests with hazards and non-robust tests. The algebra and implication tables eliminate the necessity to re-examine off-path inputs for a target path to determine the test validity. We provide examples to show that additional values at flip-flop inputs must be justified. This leads to identification of robust untestable faults without search. For the first time we present experimental results on robust and validatable non-robust test generation for ISCAS '89 sequential circuits in the non-scan mode using a variable clock scheme. Our test generator runs 26 times faster than previously published results for sequential circuits

Published in:

VLSI Design, 1997. Proceedings., Tenth International Conference on

Date of Conference:

4-7 Jan 1997