Skip to Main Content
There are a number of factors to consider when selecting an optimal semiconductor package configuration for the newer generations of high density controllers and processors; I/O requirement, package footprint, form factor, thermal dissipation, electrical performance, and cost. The more advanced microprocessor and ASIC semiconductor packaging currently require several thousand I/O contacts and they are expected to expand contact I/O by 30% in the very near future. This paper will detail the development of a unique raised contact substrate fabrication process that enables semiconductor developers to significantly reduce the contact pitch on the die without reducing pad size. The flip-chip to substrate assembly process yield is significantly higher as well because the conventional solder bumped die can be placed directly onto the raised contact features (eliminating the need for solder printing on the package substrate). Mounting the bumped die element on this planer topography solves fundamental issues associated with electro-migration and it avoids many of the current assembly process related defects. This is because the solid copper contact profile furnishes a consistent standoff height that enables a uniform and void free package interconnect as well as improving underfill flow control (even with low temperature solders).