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Development of Super Thin TSV PoP

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5 Author(s)
Carson, F. ; STATS ChipPAC, Inc., Fremont, CA, USA ; Ishibashi, K. ; Seung Wook Yoon ; Marimuthu, P.C.
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Package on Package (PoP) has emerged as the preferred method to stack logic processor and memory in more advanced mobile phone platforms. One issue with the PoP is that the overall height of the stacked package is thicker than other packages in the digital section of the phone. Reducing the thickness of the PoP solutions is important to reduce the thickness of the mobile phone and to realize the market need for thinner, sleeker products. In addition, a very thin PoP solution could enable the stacking of more than two packages on top of each other (two processor packages with shared memory package on top, for instance). This paper highlights the development of a novel, thin, PoP solution, called the Super Thin TSV PoP. In order to decrease the thickness of the PoP solution, through silicon via (TSV) interposer technology was used as the substrate of the packages. TSV interposer substrates can reduce the thickness of the substrate to 0.1mm, whereas conventional organic based substrates used for PoP are typically 0.3mm thick or more. Also, because the TSV substrate is Si based, it is matching the material property of the logic and memory device itself, thereby warpage due to the mismatch of materials should be minimized. A flip chip PoP daisy chain test vehicle was designed in order to prove the viability of this technology. This test vehicle was a 12×12mm package with 0.4mm ball pitch on the bottom and 0.4mm pitch between the top and bottom PoP package. The die sizes and bump pitch of the flip chip devices are representative and realistic of future emerging logic and memory devices. Electrical simulation was done during the design stage to assure that the layer count and routing of each PoP would meet the specifications and be comparable to future PoP designs. Thermal simulation was also performed and found to be superior to the comparable PoP configuration with organic substrate. The overall height of Super Thin TSV PoP is 0.7mm with one memory device mounted- - on the top package. More memory die-stacked on the top package and potentially higher density pitch package to package is envisioned for future implementations. This paper will highlight the development and assembly of the Super Thin TSV PoP test vehicle, challenges encountered and overcome, and future steps.

Published in:

CPMT Symposium Japan, 2010 IEEE

Date of Conference:

24-26 Aug. 2010

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