By Topic

A technology mapper for Xilinx FPGAs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
M. Y. Chikodikar ; Silicon Automation Syst., Bangalore, India ; S. Laddha ; A. Sirasao

This paper presents a method for area optimal technology mapping for Xilinx FPGAs. The method is modification of the method described previously and covers uniformly XC2000, XC3000 and XC4000 series of Xilinx FPGAs. The method addresses mapping of combinational and sequential logic onto Xilinx FPGAs. The results compare favorably with the existing mappers and the CLB estimates provided by the mapper are comparable with the CLB count obtained after passing the circuit through the Xilinx implementation kit

Published in:

VLSI Design, 1997. Proceedings., Tenth International Conference on

Date of Conference:

4-7 Jan 1997