By Topic

Macro block based FPGA floorplanning

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Shi, J. ; Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA ; Randhar, A. ; Bhatia, D.

This paper describes the floorplanning for FPGA based designs. In order to perform placement for very large designs, the currently followed approach of placing flat netlists is extremely time consuming. Also, managing large data sets, as in flat netlist files, is not trivial for performance driven designs. In this paper we describe an approach for the constraint-based FPGA floorplanning of flexible and fixed macro blocks. Our approach is to construct a floorplan of small area that respects the input constraint set. The input constraint set is derived from topological placement of the macro blocks based on both FPGA architectural constraints and ASIC design. Experimental results on FPGA floorplanning are also presented for large benchmark examples

Published in:

VLSI Design, 1997. Proceedings., Tenth International Conference on

Date of Conference:

4-7 Jan 1997