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Module miniaturization by ultra thin package stacking

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4 Author(s)
Löher, T. ; Tech. Univ. Berlin, Berlin, Germany ; Schütze, D. ; Ostmann, A. ; Aschenbrenner, R.

The scope of the European project TIPS (Thin Interconnected Package Stacks) is the fabrication of ultra thin packages for electronic components and the subsequent stacking and interconnection of those packages to form highly compact modules. In the first part of this paper approaches to fabricate ultra thin 10 × 10 mm packages by embedding technologies for chips into printed circuit board environments will be discussed. Technologies for commercial flexible printed circuit board substrates (polyimide sandwiched in Cu layers) and respective fabrication processes are used. After initial patterning of the Cu the chips are die bonded to the flex substrates and subsequently lamination into build up layers. Electrical contact between the chip and a fan out routing on the outer layer of the package are made by micro via formation, electroplating and wet chemical structuring of the metal layers. The thickness of the embedded components is constricted to 50 μm in order to constrain the package thicknesses to a maximum of 100 μm with this approach. Packages are fabricated in batches of 150 × 150 mm sheets of flex substrates. Stacking of individual packages can be performed in an automated package by package placement process using a frame as alignment tool and typical flexible printed circuit boards adhesives. In this way only known-good-packages are stacked in order to minimize yield loss. However, a more straight forward process is stacking of the packages using fabrication batches and established multilayer printed circuit board technologies. The disadvantage is the potential yield loss if one of the packages in a stacked layer is faulty. For either type of stacking process the individual stacks have to be milled out of the stack fabrication batch. After stacking and sound mechanical interconnection the electronic interconnection between layers is made by the sequence mechanical through hole drilling, plating and wet chemical structuring. Tes- - t issues, design considerations and results of first fabrication runs will be presented and discussed.

Published in:

CPMT Symposium Japan, 2010 IEEE

Date of Conference:

24-26 Aug. 2010