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Traditional test pattern generation (TPG) is a well known technique that has been used by many to generate test sequence. With increasing number of chip inputs, larger the test vector is required to ensure high fault coverage is achieved. This adds additional cost in traditional TPG generation and becomes a concern. In this paper, we introduce a new test generation method that is scalable while manages to produce high fault coverage. An attractive feature of the proposed method is it is able to sample the test signature early.