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Optimizing the Simulation Speed of QEMU and SystemC-Based Virtual Platform

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3 Author(s)
Tse-Chen Yeh ; Dept. of Comput. Sci. & Eng., Nat. Sun Yat-sen Univ., Kaohsiung, Taiwan ; Zin-Yuan Lin ; Ming-Chao Chiang

In this paper, we present a technique for optimizing the simulation speed of the QEMU and SystemC-based virtual platform.Most of the optimization methods for conventional instruction set simulator based virtual platforms focus on accelerating the simulator kernel. However, the bottleneck that affects the simulation speed of a virtual machine based virtual platform is not necessarily the simulator kernel. In order to better understand the bottleneck, we investigate the QEMU and SystemC-based virtual platform,by using it to boot up a full-fledged Linux with data movement via DMA controller model at the instruction-accurate and cycle-count-accurate levels. Based on the outcome, we propose a method to optimize its simulation speed. Compared to the original version, the optimized version can boost up the simulation speed of instruction-accurate simulator by a factor of 1.153 and the simulation speed of cycle-count-accurate simulator with different bus arbitration policies by a factor of 1.354 or 1.390,thus making the virtual platform even more suitable for electronic system level (ESL) design flow.

Published in:

Information Engineering and Computer Science (ICIECS), 2010 2nd International Conference on

Date of Conference:

25-26 Dec. 2010