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Completely Quantum–Mechanical Extraction of Equivalent Oxide Thickness of PMOS Gate Insulator

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3 Author(s)
Hiraiwa, A. ; Micro Device Div., Hitachi Ltd., Tokyo, Japan ; Shima, A. ; Ishikawa, D.

To cope with the growing problem of device variability from the viewpoint of global variability, the authors developed a completely quantum-mechanical (QM) capacitance voltage (C-V) simulator of polycrystalline-Si-gate p-channel metal-oxide-semiconductor (PMOS) devices in a similar way to the previous one for n-channel MOS (NMOS). The simulator was entirely based on experimental results and did not adopt any assumptions, which were inevitable in the other simulators, to implement the QM effects. Experimental C-V curves were almost completely reproduced by the simulator. The authors further extracted the equivalent oxide thicknesses (EOTs) of NMOS and PMOS devices, which were formed on the same dies, using this and the previous simulators. The EOTs of PMOS devices were always equal to or larger than those of the NMOS devices. The difference increased with a total dosage of fluorine atoms that were selectively introduced into the PMOS devices by BF2+ or F+ implantations during fabrication steps. It was almost zero in the case of small F dosages, as it should be. These results support the validity of this simulator. During the development of the simulator, the authors again confirmed that the relative dielectric constant of SiO2, grown at 950°C or lower, is larger than the conventional value of 3.9.

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Electron Devices, IEEE Transactions on  (Volume:58 ,  Issue: 3 )