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Power-Aware High-Level Synthesis With Clock Skew Management

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2 Author(s)
Tung-Hua Yeh ; Nat. Chung-Hsing Univ., Taichung, Taiwan ; Sying-Jyan Wang

An effective clock-skew scheduling scheme in the high-level synthesis process targeted for power and speed optimization is presented. The proposed scheme has the following distinctive features: 1) a clock-skew management algorithm that selects a minimum set of clock phases to achieve the optimization goals is developed; 2) the effect of module binding in high-level synthesis was not considered in previous studies, which may lead to designs with timing violation; a discussion on how to model the effect of module binding is provided; 3) a heuristic low-power module binding algorithm that provides near-optimal results quickly is proposed; and 4) a technique called reallocation is proposed to exploit all available skews and thus maximize the capability of clock-skew scheduling. Experimental results show that, on the average, 48% power reduction is achieved by the proposed method. At most five clock phases are required, while in most cases two to four clock phases are sufficient.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:20 ,  Issue: 1 )