In-depth profiling of electron trap states in silicon-on-insulator layers and local mechanical stress near the silicon-on-insulator/buried oxide interface in separation-by-implanted-oxygen wafers

In-depth profiling of electron trap states in silicon-on-insulator (SOI) layers of separation-by-implanted-oxygen (SIMOX) wafers was carried out using the drain current-gate voltage characteristics of metal-oxide-semiconductor field-effect transistors (MOSFETs) with different SOI thicknesses, and the density of electron trap states in a gate oxide (GOX) layer thermally grown on them was measured using the gate tunneling current-gate voltage characteristics of MOSFETs. It was found that in-depth profiles of electron trap states in SOI layers have a broad peak at around 25 nm from the SOI/buried oxide (BOX) interface, and that the density of electron trap states in a GOX layer grown on the 25-nm-thick SOI layer reaches a maximum there. A morphology study using Auger electron spectroscopy and Raman spectroscopic study revealed a correlation among the density of trap states in an SOI layer, roughness, and local mechanical stress near the SOI/BOX interface. This correlation is understood to imply that local mechanical stress near the SOI/BOX interface, which is induced by roughness at the interface peculiar to the SIMOX process, enhances the generation of structural defects and resultant electron trap states in the SOI layer of a SIMOX wafer.