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Memory-Efficient Architecture for Fast Two-Dimensional Discrete Wavelet Transform

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3 Author(s)
Xin Tian ; Dept. of Electron. & Inf. Eng., Huazhong Univ. of Sci. & Technol., Wuhan, China ; Jiaolong Wei ; Jinwen Tian

Memory-efficient architecture for fast two- dimensional Discrete Wavelet Transform(DWT) with high speed and small size of on-chip memory is proposed. It is composed of one row-wise one-dimensional(1-D) DWT module and two identical column-wise 1-D DWT modules. The input data samples are directly processed by the row-wise 1-D DWT module. This architecture reduces the size of on-chip memory and output latency. In further, the time multiplexing technology makes the column-wise 1-D DWT module process different column data samples generated from the row-wise 1-D DWT module. The proposed architecture is finally compared with the state of art architectures in terms of computing time, output latency and size of on-chip memory. The comparison results demonstrate that the proposed architecture is a high-speed architecture with less consumption of on-chip memory and shorter output latency.

Published in:

Computational Intelligence and Software Engineering (CiSE), 2010 International Conference on

Date of Conference:

10-12 Dec. 2010