By Topic

Address generation unit for multimedia applications on application specific instruction set processors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Moreno-Berengue, M. ; Univ. Autonoma de Barcelona, Bellaterra, Spain ; Talavera, G. ; Rodriguez-Alsina, A. ; Carrabina, J.

Multimedia embedded systems require high performance specific computation to process the large among of data that characterizes the multimedia domain at low energy consumption due to battery life. Different optimizations at different levels can considerably improve performance and energy consumption and, after that, the address generation becomes the new performance bottleneck. This paper shows a custom-configurable address generation unit design which extends an application specific instruction set processor (ASIP) to boost the address calculations, improving performance and reducing the energy consumption around 27%. The main innovation of our work resides in a new custom-configurable AGU design which can be automatically implemented and directly connected to the ASIP data-path. This AGU design has a fast interface which allows reading one address in only one cycle and one instruction, and calculates new values without stopping the processor. The presented design can easily be implemented in broad range of ASIPs.

Published in:

IECON 2010 - 36th Annual Conference on IEEE Industrial Electronics Society

Date of Conference:

7-10 Nov. 2010