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Reconfigurable baseband processing architecture for communication

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5 Author(s)
Lu, W.Q. ; State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China ; Zhao, S. ; Zhou, X.F. ; Ren, J.Y.
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The development of multiple communication standards and services has created the need for a flexible and efficient computational platform for baseband signal processing. Using a set of heterogeneous reconfigurable execution units (RCEUS) and a homogeneous control mechanism, the proposed reconfigurable architecture achieves a large computational capability while still providing a high degree of flexibility. Software tools and a library of commonly used algorithms are also proposed in this paper to provide a convenient framework for hardware generation and algorithm mapping. In this way, the architecture can be specified in a high-level language and it also provides increased hardware resource usage. Finally, we evaluate the system's performance on representative algorithms, specifically a 32-tap finite impulse response (FIR) filter and a 256-point fast Fourier transform (FFT), and compare them with commercial digital signal processor (DSP) chips as well as with other reconfigurable and multi-core architectures.

Published in:

Computers & Digital Techniques, IET  (Volume:5 ,  Issue: 1 )

Date of Publication:

January 2011

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