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Cone-based placement for field programmable gate arrays

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3 Author(s)
P. Banerjee ; Department of Computer Science and Engineering, University of Calcutta, 92 A.P.C. Road, Kolkata 700009, India ; D. Saha ; S. Sur-Kolay

Deterministic greedy methods have been proposed to place the netlist of configurable logic blocks (CLBs) and primary input output blocks (IOBs) quickly on a two-dimensional (2D) island-style field programmable gate array (FPGA) consisting of either one or multiple 2D island-style arrays of CLBs and IOBs. The first method, `ConeCLBPlace`, starts with a random placement of the primary output blocks along the periphery of the 2D array of CLBs, then places the CLBs and primary input blocks in a greedy deterministic way. In the second method, `ConeIOBPlace`, the IOBs are first placed on the periphery of the FPGA chip using a deterministic heuristic, and then the CLBs are placed within the 2D array using a typical simulated annealing (SA) flow. The third method, `ConePlace`, combines the above two deterministic approaches by first placing the IOBs only using ConeIOBPlace, and then the CLBs using ConeCLBPlace deterministically. Finally, a low-temperature SA is executed in order to obtain a high-quality final placement. ConeCLBPlace and ConePlace produce placements 2.34` and 1.83` faster than the placement step of popular FPGA place-and-route tool VPR (versatile place and route) on the average. The bounding box costs of placement produced by ConeCLBPlace and ConePlace, after execution of the iterative SA steps, are 1.05` and 1.14` of VPR, respectively, on the average, whereas the critical path delay obtained after routing is 1.03` of VPR for both methods on the average, implying almost the same quality of VPR. This justifies the utility of the methods proposed.

Published in:

IET Computers & Digital Techniques  (Volume:5 ,  Issue: 1 )