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Period jitter plays a critical role in global clock distribution design, because it directly impacts the time available for logic operations between sequential elements. Moreover, time-varying supply noise injected in global clock drivers can worsen the timing margin of critical paths by modulating period jitter. In the planning stage of global clock distribution for a high-end microprocessor, it is very critical to differentiate and understand the impacts of different design parameters on period jitter. However, it is hard to achieve due to complex relationship among different independent/dependent design parameters: supply noise amplitude, supply noise frequency, clock driver size, physical structures of interconnects, number of clock stages, temperature, process corners, etc. In this paper, we propose sets of analytical expressions which accurately model the behavior of supply noise induced period jitter of global binary clock trees without losing the details of clock distribution design parameters. These accurate expressions and their derivation process are used to provide detailed insight into the relationships between period jitter of binary clock distribution and distribution design parameters with several examples. Also detailed design guidelines for binary clock trees are presented.