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High-Level Synthesis of a Unified 2-D DWT System Architecture for JPEG2000 Using FPGAs

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5 Author(s)
Ishmaiel Sameen ; Fac. of Eng. Multimedia, Univ. Cyberjaya, Malaysia ; Yoong Choon Chang ; Mow Song Ng ; Bok-Min Goi
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In this paper, a programmable 2-D DWT system architecture designed for the JPEG2000 standard is proposed. The proposed system architecture, developed through an iterative design space exploration methodology using Altera's C2H compiler, provides a significant 2-D DWT performance improvement when compared to an optimized 2-D DWT software implementation and is capable of real-time video processing performance for high resolution grayscale images up to 1280 × 720 (720p) when synthesized and benchmarked in an Altera DE3 Stratix III FPGA board.

Published in:

Image and Video Technology (PSIVT), 2010 Fourth Pacific-Rim Symposium on

Date of Conference:

14-17 Nov. 2010