Referenced Items are not available for this document.
This paper presents a multiprocessor unit for fast video image data pre-processing in real time application. The author made a pipelined multiprocessor architecture from specialised hardware processors. This paper presents a reconfigurable specialised hardware processor for this pipelined architecture. The universal reconfigurable processor is implementated in Xilinx FPGA
Published in:
Signal Processing, 1996., 3rd International Conference on
(Volume:1
)
Date of Conference: 14-18 Oct 1996
- Page(s):
- 649 - 652 vol.1
- Meeting Date :
- 14 Oct 1996-18 Oct 1996
- Print ISBN:
- 0-7803-2912-0
- INSPEC Accession Number:
- 5643532
- Conference Location :
- Beijing
- Digital Object Identifier :
- 10.1109/ICSIGP.1996.567347
- Product Type:
- Conference Publications
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