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2.4-GHz 0.18-µm CMOS highly linear Power Amplifier

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3 Author(s)
Yongbing Qian ; Institute of RF- & OE-ICs, Southeast University, 210096 Nanjing, China ; Wenyuan Li ; Zhigong Wang

A Class-AB Power Amplifier (PA) integrated circuit for 2.4 GHz is presented. It is designed in SMIC 0.18 μm RF CMOS process. The PA adopts two-stage differential structure. The driver-stage uses cascode structure. In the output-stage common-source structure is employed. The proposed PA provides 24.8 dBm output power with a power-added efficiency (PAE) of 21.2% at 1 dB compression point. It has a small signal gain of 20.6 dB. The simulation results show that under a single 3.3 V supply voltage, the maximum output power reaches to 26.2 dBm. It can be used in IEEE 802.11b/g WLAN. The layout size is 1.4 × 0.75 mm2.

Published in:

The 2010 International Conference on Advanced Technologies for Communications

Date of Conference:

20-22 Oct. 2010