Referenced Items are not available for this document.
A digital random return-to-zero technique is presented to improve the dynamic performance of current-steering digital-to-analog converters (DACs). To demonstrate the proposed technique, a CMOS 8-bit 1.6-GS/s DAC was fabricated in a 90-nm CMOS technology. The DAC achieves a spurious-free dynamic range better than 60 dB for a sine-wave input up to 460 MHz and better than 55 dB up to 800 MHz. The DAC consumes 90 mW of power.
Published in:
Circuits and Systems II: Express Briefs, IEEE Transactions on
(Volume:58
,
Issue:
1
)
Date of Publication: Jan. 2011
- Page(s):
- 1 - 5
- ISSN :
- 1549-7747
- INSPEC Accession Number:
- 11762117
- Digital Object Identifier :
- 10.1109/TCSII.2010.2092823
- Product Type:
- Journals & Magazines
- Date of Publication :
- 20 December 2010
- Date of Current Version :
- 20 January 2011
- Issue Date :
- Jan. 2011
- Sponsored by :
- IEEE Circuits and Systems Society
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
