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Compact, low-voltage, low-power and high-bandwidth CMOS four-quadrant analog multiplier

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3 Author(s)
Ebrahimi, A. ; Integrated Circuits Res. Lab. (ICRL), Babol Univ. of Technol., Babol, Iran ; Naimi, H.M. ; Gholami, M.

In this paper, a new compact, low power and low voltage structure for CMOS analog multiplier is proposed. All of them are implemented using a compact circuit. The circuit is designed and analyzed in 0.18μm CMOS process model. Simulation results for the circuit with a 1.2V single supply show that it consumes only 25μw quiescent power with 2GHz bandwidth and 1.5% THD.

Published in:

Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD), 2010 XIth International Workshop on

Date of Conference:

4-6 Oct. 2010

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