Referenced Items are not available for this document.
In this paper, a new compact, low power and low voltage structure for CMOS analog multiplier is proposed. All of them are implemented using a compact circuit. The circuit is designed and analyzed in 0.18μm CMOS process model. Simulation results for the circuit with a 1.2V single supply show that it consumes only 25μw quiescent power with 2GHz bandwidth and 1.5% THD.
Published in:
Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD), 2010 XIth International Workshop on
Date of Conference: 4-6 Oct. 2010
- Page(s):
- 1 - 5
- Print ISBN:
- 978-1-4244-6816-4
- INSPEC Accession Number:
- 11698749
- Conference Location :
- Gammath
- Digital Object Identifier :
- 10.1109/SM2ACD.2010.5672341
- Product Type:
- Conference Publications
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