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Cost-Effective Power-Aware Core Testing in NoCs Based on a New Unicast-Based Multicast Scheme

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2 Author(s)
Dong Xiang ; School of Software, Tsinghua University, Beijing, China ; Ye Zhang

Reuse of network-on-chip (NoC) for test data and test response delivery is attractive. However, previous techniques do not effectively use the bandwidths of the network by delivering test packets to all cores separately, which can make very much test cost and test data volume. The NoC core testing problem is formulated as a unicast-based multicast problem in order to reduce test data delivery time in the NoC. Test response data are forwarded back to the automated test equipment (ATE) via the communication channels using the reverse paths of test data delivery, which are compacted on the way from each processor to the ATE. A new power-aware test scheduling scheme is proposed, which is extended to cases for multiple port ATEs. Test data is further compressed before delivering and a low-power test application scheme is used for the cores because power produced by cores is the bottleneck of NoC test. Experimental results are presented to show the effectiveness of the proposed method in reducing the NoC test cost and test data volume by comparing to the previous methods.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:30 ,  Issue: 1 )