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A 10-bit 100-MS/s 4.5-mW Pipelined ADC With a Time-Sharing Technique

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2 Author(s)
Yen-Chuan Huang ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Tai-Cheng Lee

A 10-bit pipelined ADC employs both opamp-and time-sharing techniques to reduce the power consumption and silicon area. The proposed ADC needs only one opamp to complete the 10-bit conversion. This ADC has been fabricated in a 90-nm digital CMOS technology and occupies only 0.058 mm2. It operates at 100 MS/s and achieves an SNDR of 55.0 dB while the power consumption is 4.5 mW from a 1.0-V supply.

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Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:58 ,  Issue: 6 )