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A dual active-capacitive-feedback compensation (DACFC) scheme for low-power three-stage amplifiers with large capacitive loads is presented in this paper. Dual high-speed active-capacitive-feedback paths enable the non-dominant complex poles of the amplifier to be located at high frequencies for bandwidth extension under low-power condition. The proposed DACFC amplifier also consists of two left-half-plane (LHP) zeros that relax the stability criteria for further improving the gain-bandwidth product (GBW) and reducing the required compensation capacitance of the amplifier. Moreover, the transient response of the DACFC amplifier is enhanced via the use of the small compensation capacitance and the presence of push-pull second and output stages. Two three-stage amplifiers using the proposed DACFC and the well-known nested Miller compensation (NMC) have been implemented in a standard 0.35-μm CMOS process. The proposed DACFC amplifier uses a total compensation capacitance of 2.2 pF and is robust in stability with a phase margin of >;58° under the variation of the load capacitance between 300 pF and 800 pF. When driving a 500-pF//25-kΩ load, the DACFC three-stage amplifier improves the GBW-to-power by 66 times, enhances the slew rate-to-power by 51 times, and reduces the chip area by 33 times, as compared to the conventional NMC counterpart.