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Novel Sub-10-nm Gate-All-Around Si Nanowire Channel Poly-Si TFTs With Raised Source/Drain

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5 Author(s)
Yi-Hsien Lu ; Dept. of Electrophys., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Po-Yi Kuo ; Yi-Hong Wu ; Yi-Hsuan Chen
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We have successfully fabricated novel sub-10-nm gate-all-around Si nanowire (NW) poly-Si TFTs with raised source/drain structure (GAA RSDNW-TFTs). The Si NW dimension is about 7×12 nm. A superior smooth elliptical shape is obtained, for the first time, in the category of poly-Si NW TFTs through the use of a novel fabrication process requiring no advanced lithographic tools. The GAA RSDNW-TFTs exhibit low supply gate voltage (3 V), steep subthreshold swing ~99 mV/dec, and high ION/IOFF >; 107 (VD = 1 V) without hydrogen-related plasma treatments. Furthermore, the DIBL of GAA RSDNW-TFTs is well controlled. These improvements can be attributed to the 3-D gate controllability, raised S/D structure, and sub-10-nm Si NW channel. These novel GAA RSDNW-TFTs are, thus, quite suitable for system-on-panel and 3-D IC applications.

Published in:

IEEE Electron Device Letters  (Volume:32 ,  Issue: 2 )