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We experimentally investigate the sensitivity of threshold voltage (T) to the variation of silicon nanowire (SiNW) width (Wsi) in gate-all-around junctionless transistors by comparison with inversion-mode transistors with the same geometric parameters. Due to the nature of junctionless transistors with a heavily doped SiNW channel, the VT fluctuation caused by the Wsi variation of junctionless transistors is significantly larger than that of inversion-mode transistors with a nearly intrinsic channel. This is because, in junctionless transistors, the channel doping concentration cannot be reduced in order to keep their inherent advantages. Therefore, our findings indicate that careful optimization or methods to mitigate the VT fluctuation related to the Wsi variation should be considered in junctionless transistors.