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As interest mounts in using hardware accelerators to speed up numerical scientific calculations, automation tool support is required to aid designers in mapping applications to custom hardware. One key step in designing this custom hardware is bit-width allocation where the known-art faces challenges when dealing with applications from the scientific computing domain, thus motivating the use of computational methods based on Satisfiability-Modulo Theory. Many real-life applications are, however, specified in terms of vectors and matrices which are of sufficient size to make expansion into scalar equations infeasible. The proposed vector-magnitude method and its extension via block vectors enable computational methods to be leveraged in tackling calculations of practically relevant complexity. Application to case studies confirms that through a more compact computational instance, search efficiency is improved leading to tighter bounds and thus smaller bit-widths.