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Source/drain and gate engineering on Si nanowire transistors with reduced parasitic resistance and strained silicon channel

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5 Author(s)
Toshinori Numata ; Advanced LSI Technology Laboratory, Corporate R&D Center, Toshiba Corporation, 8 Shinsugita-cho Isogo-ku, Yokohama 235-8522, Japan ; Masumi Saitoh ; Yukio Nakabayashi ; Kensuke Ota
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We successfully achieved the reduction of the parasitic resistance and the mobility enhancement in Si nanowire transistors (NW Tr.) by raised source/drain extensions with thin spacer (<;10nm) and by stress induced from heavily-doped gate. Id variations are suppressed by the spacer thinning. By adopting <;100> NW channel instead of <;110> NW, Ion = 1 mA/μm for Ioff = 100 nA/μm is achieved without stress techniques. Parasitic capacitance increase due to the spacer thinning is minimal. Heavily-doped poly-Si gate induces vertically compressive strain in NW, lon increase of 43% is achieved by the additive strain effect of heavily-doped poly-Si gate and tensile stress liner.

Published in:

Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on

Date of Conference:

1-4 Nov. 2010