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Improved delay fault coverage in SoC using controllable multi-Scan-Enable

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4 Author(s)
Jin-yi Zhang ; Key Lab. of Adv. Displays & Syst. Applic., Shanghai Univ., Shanghai, China ; Xu-hui Huang ; Wan-lin Cai ; Han-yi Weng

This paper presents a method of multi-Scan-Enable DFT design for at-speed scan testing to improve transition fault coverage. Base on the method, we build a novel TR-TC (Test Resources-Test Coverage) associated test cost mathematical model to effectively control the complexity of at-speed DFT design and establish the optimization number of Scan-Enable, which provides a reliable target control value in multi-Scan-Enable DFT design for at-speed scan testing. Experiment results for transition fault coverage improvement on three industrial SoC circuits and the upper limit of the number of Scan-Enable are presented.

Published in:

Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on

Date of Conference:

1-4 Nov. 2010