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Energy efficiency plays an important role in the design of high performance analog CMOS circuits. In medium- to high accuracy circuits, it is becoming increasingly difficult to maintain energy efficiency as CMOS technology is scaled to nanometer dimensions. This paper discusses some of the important challenges often faced by analog designers working with nanoscale CMOS technologies and reviews state-of-the-art circuit level techniques that can be utilized to mitigate the impact of technology scaling on energy efficiency.
Date of Conference: 1-4 Nov. 2010