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Design and verification of Distributed RAM using Look-Up Tables in an SOI-based FPGA

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5 Author(s)
Xiaowei Han ; Inst. of Semicond., Chinese Acad. of Sci., Beijing, China ; Chen, S.L. ; Lihua Wu ; Yan Zhao
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A novel architecture of the configurable Distributed Random Access Memory (RAM) logic based on Look-Up Tables (LUTs) in the Logic Block (LB) is proposed and implemented in a tile-based FPGA manufactured with a 0.5μm SOI-CMOS logic process. The Distributed RAM can be configured in two modes: Single-Port RAM and Dual-Port RAM. Due to its resource abundance and low latency the Distributed RAM can complement Block RAM in implementing the data storage logic of many applications. The functionality and performance of the Distributed RAM have been proven in our test circuit. Comparing with the published data on the Distributed RAM in Xilinx Spartan FPGA, our Distributed RAM average access time has about 21% improvement.

Published in:

Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on

Date of Conference:

1-4 Nov. 2010