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Bandwidth-efficient architecture design for Motion Compensation in H.264/AVC Decoder

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4 Author(s)
Chung-Fu Lin ; Core Technology Development Division, No.5, Li-Hsin Rd. III, Hsinchu Science Park, Taiwan 300, R.O.C. ; Chang-Chin Chung ; Yuan-Chieh Tsai ; Yu-Sen Ou

In this work, a Block-Clustering Based (BCB) method is proposed to reduce the memory access number of Motion Compensation (MC) in H.264/AVC Decoder. By grouping the possible 4 × 4 blocks within one Macroblock (MB) to share the loaded reference data, the memory access number can be significantly reduced around 70% in average. Moreover, to reduce the precharge/active frequency during SDRAM accessing, a command-reordering method is adopted to achieve 60% reduction in average. In our simulation, the total memory access number for processing one MB is less than 400 cycles. This method is scalable to different internal memory size used in MC hardware design.

Published in:

Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on

Date of Conference:

1-4 Nov. 2010