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This paper presents a 12-bit 50-MS/s pipelined Analog-to-Digital Converter (ADC) in a 65-nm 1P7M CMOS process. A hybrid architecture is selected to make a trade-off between the power dissipation and performance of the ADC. For subsampling application, a wideband Sample and Hold Circuit (SHC) is proposed, including a high-linearity input switch and a two-stage operational amplifier (opamp) with hybrid cascode compensation. Some optimization methods for design of Multiplying Digital-to-Analog Converter (MDAC) are also adopted. Simulation results show that the ADC maintains over 82 dB SFDR and 71 dB SNDR for input signal up to Nyquist range. The ADC consumes 53.8 mW at sampling rate of 50 MHz from 1.2-V supply voltage, and achieves a FOM value of 0.35 pJ/step.