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A successive approximation register analog-to-digital converter(SAR ADC) targeted for use in RSSI(received signal strength indicator) is presented. The measured signal-to-noise-and-distortion ratios(SNDR) of the ADC is 53.95 dB at 1MS/s sampling rate with power consumption of 147.6 μW from 1.2-V supply voltage, thus the resulting FOM is 0.437 pJ/conversion-step. The ADC is fabricated in a 0.13-μm technology.
Published in:
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Date of Conference: 1-4 Nov. 2010
- Page(s):
- 569 - 571
- Print ISBN:
- 978-1-4244-5797-7
- INSPEC Accession Number:
- 11697112
- Conference Location :
- Shanghai
- Digital Object Identifier :
- 10.1109/ICSICT.2010.5667328
- Product Type:
- Conference Publications
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