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A successive approximation register analog-to-digital converter(SAR ADC) targeted for use in RSSI(received signal strength indicator) is presented. The measured signal-to-noise-and-distortion ratios(SNDR) of the ADC is 53.95 dB at 1MS/s sampling rate with power consumption of 147.6 μW from 1.2-V supply voltage, thus the resulting FOM is 0.437 pJ/conversion-step. The ADC is fabricated in a 0.13-μm technology.
Date of Conference: 1-4 Nov. 2010