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This paper presents an overview of the technological challenges facing the future scaling of device dimensions needed to meet the performance scaling in accordance with Moore's law. A number of performance boosters have to be introduced in order to keep up with the expected performance gain in each new technology node. The introduction of strain engineering is an important feature as well as the implementation of high-k dielectrics. From the 32 nm node and forward there is an urgent search for a fundamental breakthrough to achieve low access resistance to the drain and source areas. This paper will focus to a large extent on this latter area and discuss metallic source/drain (MSD) contacts in nanoscaled MOSFET technology. MSD contacts offer extremely low S/D parasitic resistance, abruptly sharp junctions between S/D and channel and preferably low temperature processing. Recently great efforts have been achieved on Pt- and Ni-silicide implementation. A conclusion is that MSD MOSFETs are competitive candidates for future generations of CMOS technology.