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The BIST Aided Scan Test (BAST) is a technique that combines the automatic test pattern generator (ATPG) and the Built-In-Self-Test (BIST) to reduce test data volume while maintaining high test quality. On BAST architecture, a bit-flipping technique is used to convert pseudo-random patterns to deterministic patterns. In this paper, we propose a don't care identification technique for random-pattern-resistant faults to identify unnecessary signal values to detect a fault set as don't care bits. Random-pattern-resistant faults are defined as the number of detection for each fault by a given test pattern set, this number is equal to or less than N. We also propose a matching method of between a pseudo-random pattern set and a deterministic pattern set for random-pattern-resistant faults to which the don't care identification technique is applied. We apply the proposed method to ITC'99 benchmark circuits and show that the proposed method effectively reduces the number of bit-flips and test application times. We also evaluate the relationship among the number of random-pattern resistant faults, the number of don't care bits, the number of undetected faults, the number of bit-flips, and test application time.