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A time-multiplexed reconfigurable neuroprocessor

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2 Author(s)
Sibai, F.N. ; Intel Corp., USA ; Kulkarni, S.D.

Built around biological-like information-processing structures, artificial neural networks (ANNs) have demonstrated their power and usefulness in areas where identification and adaptability are most crucial. After sufficient training with a given set of problem data (using an arbitrary learning rule), ANNs can independently form internal representations (models) of the data's underlying phenomenon. ANNs typically have a large number of highly interconnected processing elements, which constrains their hardware implementation and network architecture. To obtain high density and processing-element connectivity, most ANN architectures employ some kind of resource sharing. A multilayer structure allows processing elements to share communication lines and control circuitry, so we chose to develop a multilayered neuroprocessor based on pipelined time-step interneural communication. Other pulse stream architectures use the rate of impulses to represent the neural states. Our architecture, however, represents the neural states through pulse amplitude modulation. Also, in our design, the analog computation consists of integrating the bipolar input pulses corresponding to the excitatory and inhibitory activations. The processing-element analog path consists. of CMOS transmission gates controlled by buffered signals originating from the neuroprocessor control unit. The processing elements broadcast their output states, held on a local capacitor, during their assigned time slots. These features are desirable to meet the design goals of versatility, high density, high connectivity, and scalability

Published in:

Micro, IEEE  (Volume:17 ,  Issue: 1 )