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The AC power supply clocked circuits is a class of digital gates which uses clock signals replacing the VDD and ground terminals in the static gates. In this paper the guideline for an AC-clocked logic gate is described. One crucial problem related to digital circuits design is the zero-order calculation or first guess on the device dimensions. The DCVSL-Differential Cascode Voltage Switching Logic in CMOS technology is a critical circuit if the designer has restricted specification such as maximum operational frequency, load or fan-out. This paper shows a detailed design methodology for DCVSL which is also useful for other circuit and configurations. The XNOR gates with three inputs were designed under frequency and load restrictions. A few design rules were established allowing the designer a great knowledge in the circuit operation and performance optimization. As a result, the design rules were validated by simulation tools such as ADS-Advanced Design System, and the complete layout generated on 0.35 μm CMOS technology for further integration. A Full Adder circuit layout was also implemented on CMOS technology. The comparison between the AC-clocked circuit and the DC-power supply circuit shows that there is effective energy consumption favorable to the AC-clocked gate.