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This paper presents an integrated CMOS switching power converter that accommodates adaptive wireless powering scheme in biomedical implants. It employs the techniques of dual-loop error correction, observation-based oversampling, and Δ- Σ modulation to enhance transient response, line/load regulation, and noise suppression performance. By adopting a digital filter for proportional-derivative compensation, fully on-chip frequency compensation is achieved. In addition, a double sampling technique is introduced to improve the signal processing speed. The converter was designed and fabricated with a 130-nm CMOS process. The measurement results demonstrate 23.2/20.4-μs up-/down-tracking times to full-range reference voltage step changes. A 28.5-mV/V line regulation is achieved, when the supply voltage varies from 1.15 to 1.50 V. In addition, with a 1.20-V supply, the converter responds to a 10%-to-100% load current step change within 22.1 μs. A maximum efficiency of 95.5% is measured at 0.90-V output voltage and 45-mW output power. Noise power spectrum demonstrates a 100-dB signal-to-noise ratio in the converter.
Date of Publication: Sept. 2011