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Synthesis of low-power selectively-clocked systems from high-level specification

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4 Author(s)
Benini, L. ; Comput. Syst. Lab., Stanford Univ., CA, USA ; Vuillod, P. ; De Micheli, G. ; Coelho, C.

In this paper we propose a technique for synthesizing low-power systems from a high-level specification. We analyze the control flow of the specification to detect mutually exclusive sections of the computation. A selectively-clocked interconnection of interacting FSMs is automatically generated and optimized where each FSM controls the execution of one section of computation. Only one of the interacting FSMs is active at any given clock cycle, while all the others are idle and their clock is stopped. Our interacting FSM implementation achieves consistently lower power dissipation than the functionally equivalent monolithic implementation. On average 37% power savings are obtained with a 30% area overhead

Published in:

System Synthesis, 1996. Proceedings., 9th International Symposium on

Date of Conference:

6-8 Nov 1996