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Performance evaluation of a RISC neuro-processor for neural networks

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3 Author(s)
Kumar, S. ; Dept. of Electr. & Electron. Eng., Melbourne Univ., Parkville, Vic., Australia ; Forward, K. ; Palaniswami, M.

In this paper design details of a RISC neuro-processor are presented. Neural network applications of Hopfield networks, self-organizing feature maps and multilayer feedforward networks (MFNN) are used as benchmarks for performance evaluation of the neuro-processor. Extensive simulations have been carried out to study the cost performance issues of neuro-processor hardware architecture. A quantitative approach is employed in designing cost-effective implementation of the neuro-processor. Special instructions have been provided in the neuro-processor instruction-set to improve the speed of both implementation and execution of neural networks. Instruction-set usage measurements have been used to study the effectiveness of the instruction-set design. Branch behaviour statistics have been studied in order to adopt good branch prediction strategies

Published in:

High Performance Computing, 1996. Proceedings. 3rd International Conference on

Date of Conference:

19-22 Dec 1996