By Topic

GA-based floorplan-aware topology synthesis of application-specific network-on-chip

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Guoming Lai ; Sch. of Inf. Sci. & Technol., Sun Yat-sen Univ., Guangzhou, China ; Xiaola Lin ; Siyan Lai

Application-specific SoC requires an efficient interconnection topology which does not necessarily conform to regular topologies such as mesh etc. As NoC topology synthesis is an NP-hard problem, we present a genetic-algorithm (GA) based technique to synthesize application-specific NoC topology with system-level floorplan aware. The technique minimizes the power consumption and router resources while satisfying latency and bandwidth performance constraints. We validate our technique by showing the results of several benchmark applications. The proposed technique generates optimal topology within few minutes.

Published in:

Intelligent Computing and Intelligent Systems (ICIS), 2010 IEEE International Conference on  (Volume:2 )

Date of Conference:

29-31 Oct. 2010