By Topic

Incorporating fault tolerance in superscalar processors

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Franklin, M. ; Dept. of Electr. & Comput. Eng., Clemson Univ., SC, USA

In this paper, we investigate techniques to incorporate fault tolerance in superscalar processors, the de facto execution model for building processors today. We first analyze the different ways in which errors can manifest when faults occur in various parts of a superscalar processor. We then describe different ways of detecting and recovering from these errors, and the merits and demerits of these schemes. Finally, we present the results of a simulation study conducted to determine the performance loss incurred due to the introduction of these fault tolerance schemes. These results suggest that fault tolerance can be incorporated in superscalar processors, with low hardware overhead, low performance overhead, and good error coverage

Published in:

High Performance Computing, 1996. Proceedings. 3rd International Conference on

Date of Conference:

19-22 Dec 1996