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Design of a Low-Power Coprocessor for Mid-Size Vocabulary Speech Recognition Systems

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2 Author(s)
Peng Li ; Electr. & Comput. Eng. Dept., Univ. of Minnesota Duluth, Duluth, MN, USA ; Hua Tang

Speech recognition systems have gained popularity in consumer electronics. This paper presents a custom-designed coprocessor for output probability calculation (OPC), which is the most computation-intensive processing step in continuous hidden Markov model (CHMM)-based speech recognition algorithms. To save hardware resource and reduce power consumption, a polynomial addition-based method is used to compute add-log instead of the traditional look-up table-based method. In addition, the optimal tradeoff between speech processing delay, energy consumption, and hardware resources is explored for the coprocessor. The proposed coprocessor has been implemented and tested in Xilinx Spartan-3A DSP XC3SD3400A, and also validated using the standard-cell-based approach in IBM 0.13 μm technology. To implement an entire speech recognition system, SAMSUNG S3C44b0X (containing an ARM7) is used as the micro-controller to execute the rest of speech processing. Tested with a 358-state 3-mixture 27-feature 800-word HMM, S3C44b0X operates at 40 MHz and coprocessor at 10 MHz to meet the real-time requirement, and the recognition accuracy is 95.2%. Power consumption of the micro-controller is 10 mW, and that of the coprocessor 15.2 mW. The overall speech recognition system achieves the lowest energy consumption per word recognition among many reported designs. Experiment and analysis show that the speech recognition system based on the proposed coprocessor is especially suitable for mid-size vocabulary (100-1000 words) recognition tasks.

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Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:58 ,  Issue: 5 )