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Design of Digital Circuits Using Inverse-Mode Cascode SiGe HBTs for Single Event Upset Mitigation

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8 Author(s)
Thrivikraman, T.K. ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; Wilcox, E. ; Phillips, S.D. ; Cressler, J.D.
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We report on the design and measured results of a new SiGe HBT radiation hardening by design technique called the “inverse-mode cascode” (IMC). A third-generation SiGe HBT IMC device was tested in a time resolved ion beam induced charge collection (TRIBICC) system, and was found to have over a 75% reduction in peak current transients with the use of an n-Tiedown on the IMC sub-collector node. Digital shift registers in a 1st-generation SiGe HBT technology were designed and measured under a heavy-ion beam, and shown to increase the LET threshold over standard npn only shift registers. Using the CREME96 tool, the expected orbital bit-errors/day were simulated to be approximately 70% lower with the IMC shift register. These measured results help demonstrate the efficacy of using the IMC device as a low-cost means for improving the SEE radiation hardness of SiGe HBT technology without increasing area or power.

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Nuclear Science, IEEE Transactions on  (Volume:57 ,  Issue: 6 )