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A fast binary adder with conditional carry generation

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1 Author(s)
Lo, J.-C. ; Dept. of Electr. & Comput. Eng., Rhode Island Univ., Kingston, RI, USA

This paper presents a fast binary adder in static CMOS realization. While the carry derivation is similar to that in a conditional-sum adder, the proposed adder is also similar to that of a spanning tree carry lookahead adder in the sense that only selected carry bits are generated and the sum bits are produced by carry-select adders. In a 1.2 μm static CMOS realization, the proposed adder adds two 32-bit operands in 3.28 ns. This delay is measured from the assertion of the input to the arrival of the slowest sum bit

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Computers, IEEE Transactions on  (Volume:46 ,  Issue: 2 )